A roadmap for the next decade of chips

Imec is the world's leading semiconductor research company, and it recently shared its sub-1-nanometer silicon and transistor roadmap at the ITF World event held in Antwerp, Belgium. The roadmap provides insights into the company's collaboration with industry giants such as TSMC, Intel, Nvidia, AMD, Samsung, and ASML for the development of the next major process nodes and transistor architectures until the year 2036. The company also outlined the transition towards what it calls CMOS 2.0, involving the decomposition of chip functional units (such as L1 and L2 cache) into more advanced 3D designs compared to current small-chip-based approaches.

Just a reminder, 10 angstroms is equal to 1 nanometer. Therefore, Imec's roadmap includes sub-1-nanometer process nodes. The roadmap outlines that standard FinFET transistors will continue until 3nm, followed by a transition to a new nanosheet design with Gate-All-Around (GAA) architecture, which is set to enter mass production in 2024. Imec has mapped out the roadmap for 2nm and A7 (0.7nm) Forksheet designs, followed by breakthrough designs such as CFET for A5 and A2, incorporating atomic channels.

Over time, the transition to these smaller nodes has become increasingly expensive, and the conventional approach of building a single-chip per wafer has given way to chiplets. Chiplet-based designs break down various chip functions into interconnected, distinct chips, allowing the chip to function as a cohesive unit—though trade-offs are necessary.

Imec envisions the CMOS 2.0 paradigm, which involves breaking down the chip into smaller segments, separating cache and memory into units with different transistors, and then stacking them in a 3D arrangement above other chip functionalities. This approach will heavily rely on Backside Power Delivery Network (BPDN), a network routing all power through the backside of the transistors.

Let's take a closer look at Imec's roadmap and the new CMOS 2.0 approach.

As you can see in the gallery above, with the progress of nodes, the industry faces seemingly insurmountable challenges. However, the demand for more computing power, especially for machine learning and artificial intelligence, is experiencing exponential growth. Meeting this demand is no easy feat. Costs are soaring, and the power consumption of high-end chips is steadily increasing. Power scaling remains a challenge, as CMOS operating voltages stubbornly resist going below 0.7 volts. The continuous need for expansion to larger chips brings power and cooling challenges that will require entirely new mitigation solutions.

While the number of transistors continues to double along the predictable Moore's Law trajectory, other fundamental issues are increasingly becoming challenges with each new generation of chips. For instance, limitations in interconnect bandwidth significantly lag behind the computational capabilities of modern CPUs and GPUs, hindering performance and restricting the effectiveness of these additional transistors.

Imec Transistor and Process Node Roadmap

However, the primary focus is on faster and denser transistors, and the first wave of these transistors will accompany the debut of Gate-All-Around (GAA)/Nanosheet devices at the 2nm node in 2024, replacing the FinFET technology that currently powers leading-edge technologies. GAA transistors endow improvements in transistor density and performance, such as faster transistor switching, while using the same drive current as multiple fin devices. Leakage is also significantly reduced as the channel is entirely surrounded by the gate, and adjusting the thickness of the channel can optimize power consumption or performance.

We have seen several chip manufacturers adopt different variants of this transistor technology. Industry leader TSMC plans to commence mass production of its GAA-based N2 node in 2025, making it the last to adopt the new transistor. Intel, with its "Intel 20A" process node, employs a four-layer RibbonFET with four stacked nanosheets, each fully surrounded by a gate, set to debut in 2024. Samsung is the first to produce GAA for shipping products, but the limited-volume SF3E pipe-clean node won't see mass production. Instead, the company will launch its advanced nodes for high-volume manufacturing in 2024.

Just a reminder, 10 angstroms (A) is equal to 1 nanometer (nm). This means that A14 is 1.4 nanometers, A10 is 1 nanometer, and we are expected to enter the sub-1-nanometer era with A7 within the timeframe of 2030. However, please bear in mind that these metrics often do not directly correspond to the actual physical dimensions on the chip.

Imec anticipates Forksheet transistors ranging from 1nm (A10) down to the A7 node (0.7nm). As depicted in the second slide, this design involves stacking NMOS and PMOS separately but with the use of dielectric barriers to keep them apart, thereby achieving higher performance and or improved density.

Complementary FET (CFET) transistors will further reduce the footprint when they first appear at the 1nm node (A10) in 2028, allowing for a more compact standard cell library. Ultimately, we will witness CFET versions with atomic channels, enhancing performance and scalability even further. CFET transistors (you can read more about them here) stack N-type and PMOS devices together to achieve higher density. CFET is expected to mark the conclusion of nanosheet device scaling and the visible end of the roadmap.

However, breaking the barriers of performance, power, and density scaling will require additional crucial technologies. Imec envisions that this will necessitate a new CMOS 2.0 paradigm and System Technology Co-optimization (SCTO).

STCO and Backside Power Delivery

At the highest level, System Technology Co-optimization (STCO) requires a rethinking of the design process by modeling the requirements of the system and target applications. Then, utilizing this knowledge to inform design decisions for creating chips. This design approach often leads to the 'decomposition' of functional units typically part of a single-chip processor, such as power delivery, I/O, and high-speed cache. These units are then separated into individual entities, optimizing the transistors for the desired performance characteristics using different approaches for each unit type, which in turn increases costs.

One of the goals of completely decomposing the standard chip design is to split the high-speed cache/memory into their own separate layers in a 3D stacking design (more details below). However, this necessitates reducing complexity at the top of the chip stack. The transformation of the Back End of Line (BEOL) production process, with a focus on connecting transistors together and achieving communication (signal) and power transmission, is crucial for this work.

Differing from designs today that transmit power from the top down to transistors, the Backside Power Distribution Network (BPDN) utilizes Through-Silicon Vias (TSVs) to route all power directly to the backside of transistors. This effectively separates power transmission from data interconnects residing within. Placing power circuitry and data interconnects apart improves voltage drop characteristics, allowing for faster transistor switching, while achieving more dense signal routing at the top of the chip. There are also benefits to signal integrity, as simplified wiring can connect resistors and capacitors more rapidly.

Moving the power distribution network to the bottom of the chip allows for easier wafer-to-wafer bonding at the top of the bare die, unlocking the potential for logic stacked on top of memory. Imec even envisions the possibility of relocating other functions to the backside of the wafer, such as global interconnects or clock signals.

Intel has announced its version of BPDN technology, named PowerVIA, which is set to debut at the intel 20A node in 2024. Intel will reveal more details about this technology at the upcoming VLSI event. Meanwhile, TSMC has also announced the introduction of BPDN in its N2P node, scheduled for mass production in 2026, putting this technology significantly behind Intel's by quite a margin. There are also rumors that Samsung will adopt this technology at its 2nm node.

CMOS 2.0: The True path to 3D chips

CMOS 2.0 represents imec's pinnacle vision for the future of chip design, encompassing full 3D chip architecture. While we have already seen AMD's second-generation 3D V-Cache, which stacks L3 memory on top of processors to enhance memory capacity, imec envisions the entire cache hierarchy housed in its own layer. This involves vertically stacking L1, L2, and L3 caches on their own chip above the transistors constituting the processing core. Each level of the cache will be created using transistors most suitable for that task. This means utilizing older nodes for SRAM, as the scaling of SRAM has significantly slowed down.

This is becoming increasingly important. The diminishing scale of SRAM has resulted in caches occupying a higher proportion of the bare die, leading to an increase in cost per megabyte and hindering chip manufacturers from utilizing larger caches. Therefore, the cost reduction associated with moving 3D stacked caches to lower-density nodes could potentially lead to larger caches than what we have seen in the past. If implemented correctly, 3D stacking can also help alleviate latency issues associated with larger caches.

These CMOS 2.0 technologies will utilize 3D stacking techniques, such as wafer-to-wafer hybrid bonding, to form direct chip-to-chip 3D interconnects.

As you can see in the album above, Imec also has a 3D-SOC roadmap outlining the continuous shrinking of interconnects by integrating 3D designs, aiming to achieve faster and denser interconnections in the future. These advancements will be realized in the coming years through the use of updated types of interconnects and processing methods.