About What The Chip's 7nm Is

The following is a small edition from the Internet found a classic logic chip structure profile. As you can see from the figure, the structure of the semiconductor chip/device is very complex and is composed of many layers of structure superimposed:

The bottom FOEL(Front End of Line) is the transistor structure

The BOEL(Back End of Line) above it is a part of the structure that connects each transistor with a metal wire (mainly copper wire)

The top is the part that leads out the signal and power pins. This part is usually not processed in the wafer factory, but in the packaging plant

The structure of the transistor /MosFET is actually changing. In general, up to 28nm, the structure of the transistor is usually the Planar structure in the figure below: the planar structure. Starting from 20nm, the transistor has entered the era of three-dimensional structure, the most typical is the FinFET structure in the following figure. The confusion about the concept of crystal pipeline width also starts from here

Generally, the so-called line width, the standard name in the industry is CD/Critical Dimention, and the Chinese direct translation is the feature size. It refers to the smallest line width in the chip structure, usually the length of the gate (see far left below).

Later, the length of the gate is no longer the minimum line width and cannot accurately represent the process node. Therefore, the industry began to use the minimum line width half-distance to represent the line width, which is half of the distance between the center of the two smallest adjacent lines in all graphics. This number represents the highest graphics resolution in the chip architecture

The resolution in the technical parameters of the current lithography machine is actually the half spacing of this smallest line (see the middle of the following figure).

However, in the era of FinFET process, it is actually limited to the technical capability of the lithography machine. The actual graphic resolution we can achieve has not been greatly improved, but the actual density of the transistor has indeed been greatly improved after the change in the structure of the transistor. Then how to evaluate its technological level?

So, the fabs "brainwave", came up with the concept of equivalent line width.

Below is the standard transistor density calculation method published in Intel's technical documentation. In simple terms, the primary transistor density is calculated using the area of a standard and not gate (containing 4 transistors), and then the average primary transistor density is calculated using a standard FlipFlop flip-flop (containing 6 and not gates) circuit. The two density results are then weighted to average to find the number of transistors that can be made per unit area of the wafer under current technology.

This density value is then compared to the density of the planar transistor, and the equivalent line width value is calculated. Therefore, although we can not greatly reduce the actual graphic line width, we can reduce the area of the transistor and increase the density by changing the device structure to obtain an equivalent "small line width".

Starting with the 20nm FinFET process, this is true for all the so-called line widths we see.

Of course, due to the use of equivalent conversion method, this provides an opportunity for each wafer factory to fish in troubled waters. Using algorithmic opportunism, the actual transistor density of each so-called same process node chip is different, and the difference is not small.

As can be seen from the following figure: although it is also called a 10nm node, Intel's transistor density has achieved 106 million/square millimeters, while the density of TSMC and Samsung is only 0.53 and 0.52, almost double the difference.

At the subsequent 7nm\5nm node, the same situation still exists. It can be seen that on the name, honest Intel suffered a big loss and was bullied by the other two.

Since the naming of process nodes is unreliable, what method is used in the industry to measure the level of capability of a specific process?

In fact, there are many indicators used to judge the specific process technology in the FinFET process, but in most cases, we remember and understand two terms:

1) CPP: Contacted Poly Pitch gate spacing of the contact holes 2) MxP: Metal Pitch wire spacing (usually refers to the first or second layer wire spacing).

CPP reflects the width of the entire transistor CELL; MxP is a unit used to measure the height of a transistor unit, often referred to as Track. The height of the transistor is several times that of the MxP, which is called a few tracks, or a few T's.

These two indicators represent the size of the transistor, which is equal to determining the density per unit area of the transistor. Here's a reference:

 

In addition, another indicator is the Fin Pitch. The ratio of M2P to Fin Pitch is called the Gear Rate.

Well, seeing here you generally have a general understanding of the line width in advanced technology.