Advanced packaging basic terms

2.5D packaging represents a significant technological advancement in the "More than Moore" era. As chip miniaturization becomes increasingly difficult and costly at each process node, engineers have turned to advanced packaging to integrate multiple chips without the need for further chip scaling. This article will provide a brief introduction to the ten most common terms in advanced packaging technology.

2.5D packaging

2.5D packaging

2.5D packaging is an advancement over traditional 2D IC packaging technology, enabling finer circuitry and spatial utilization. In 2.5D packaging, bare die stacks or side-by-side placement occur on top of an interposer layer with through-silicon vias (TSVs). The interposer layer, acting as the base, facilitates connectivity between the chips.

2.5D packaging is commonly used in high-end ASICs, FPGAs, GPUs, and memory cubes. In 2008, Xilinx partitioned its large FPGAs into four smaller chips with higher yields and interconnected these chips via a silicon interposer. Thus, 2.5D packaging was born and eventually widely adopted for High Bandwidth Memory (HBM) processor integration.

▲2.5D封装示意图

3D packaging

In 3D IC packaging, logic bare die stacks are stacked together or combined with memory bare die stacks, eliminating the need for constructing large System-on-Chip (SoC) monoliths. Connectivity between the bare die is achieved through an active interposer layer. While 2.5D IC packaging utilizes conductive bumps or Through-Silicon Vias (TSVs) to stack components on the interposer layer, 3D IC packaging connects multiple layers of silicon wafers with TSV-enabled components.

TSV technology is a crucial enabling technology in both 2.5D and 3D IC packaging. The semiconductor industry has been using HBM (High Bandwidth Memory) technology to produce DRAM chips for 3D IC packaging.

▲From the cross-sectional diagram of 3D packaging, it can be observed that vertical interconnects between silicon chips are achieved through metal copper TSVs.

Chiplet

In the chip library, there is a range of modular chips that can be integrated into packaging using die-to-die interconnect technology. Chiplets represent another form of 3D IC packaging, enabling heterogeneous integration of CMOS and non-CMOS components. In other words, they are smaller-scale SoCs, also referred to as chiplets, as opposed to large SoCs within the package.

Breaking down large SoCs into smaller chiplets offers higher yields and lower costs compared to single-die solutions. Chiplets allow designers to leverage various IPs without concern for which process node or manufacturing technology to adopt. They can be manufactured using a variety of materials, including silicon, glass, and laminates.

▲A Chiplet-based system consists of multiple chiplets on an interposer layer.

Fan-Out Packaging

In Fan-Out packaging, the "connections" are fanned out on the surface of the chip, providing more external I/O. It employs epoxy molding compound (EMC) to fully embed the bare die, eliminating the need for processes such as wafer bumping, underfill, flip-chip bonding, cleaning, bottom encapsulation, and curing, thus avoiding the need for an interposer layer and simplifying heterogeneous integration.

Compared to other packaging types, Fan-Out technology offers smaller form factors with more I/O. In 2016, it enabled Apple to integrate its 16-nanometer application processor with mobile DRAM using TSMC's packaging technology into a single package for the iPhone 7, making it a technological standout.

▲Fan-out package

Fan-out wafer-level Package (FOWLP)

FOWLP technology is an improvement on wafer-level packaging (WLP) to provide more external connectivity to silicon chips. It embeds the chip into an epoxy resin molding material, then constructs a high density redistribution layer (RDL) on the wafer surface and applies solder balls to form a reconstituted wafer.

It usually first cuts the treated wafer into a single bare crystal, then scatters the bare crystals onto a carrier structure and fills the gaps to form a reconstructed wafer. FOWLP provides a lot of connectivity between the package and the application board, and since the substrate is larger than the bare crystal, the bare crystal spacing is actually looser.

FOWLP technology is an improvement on wafer-level packaging (WLP) to provide more external connectivity to silicon chips. It embeds the chip into an epoxy resin molding material, then constructs a high density redistribution layer (RDL) on the wafer surface and applies solder balls to form a reconstituted wafer.

It usually first cuts the treated wafer into a single bare crystal, then scatters the bare crystals onto a carrier structure and fills the gaps to form a reconstructed wafer. FOWLP provides a lot of connectivity between the package and the application board, and since the substrate is larger than the bare crystal, the bare crystal spacing is actually looser.

▲FOWLPEncapsulation example

Integrating different components manufactured separately into higher-level components enhances functionality and improves working characteristics, so semiconductor component manufacturers are able to combine functional components with different process flows into a single component.

Heterogeneous integration is similar to system-level encapsulation (SiP), but instead of integrating multiple bare crystals on a single substrate, multiple ips are integrated on a single substrate in the form of Chiplet. The basic idea of heterogeneous integration is to combine multiple components with different functions in the same package.

▲Some technical construction blocks in heterogeneous integration

HBM

HBM is a standardized stack storage technology that provides high-bandwidth channels for data within the stack, as well as between memory and logical components. HBM packages stack memory bare crystals and connect them together via TSV to create more I/O and bandwidth.

HBM is a JEDEC standard that vertically integrates multiple layers of DRAM components in a package, along with application processors, Gpus, and SOCs. HBM is mainly implemented in the form of 2.5D packages for high-end servers and networking chips. The current HBM2 release addresses the capacity and clock rate limitations in the original HBM release.

▲HBM封装

Intermediate layer

The intermediate layer is the pipe that transmits the electrical signal of the multi-chip bare crystal or circuit board in the package, and is the electrical interface between the jack or connector, which can spread the signal further and can also be connected to other jacks on the board.

The intermediate layer can be made of silicon and organic materials and acts as a bridge between multiple bare crystals and the circuit board. Silicon intermediate layer is a proven technology with high fine-pitch I/O density and TSV formation capability that plays a key role in 2.5D and 3D IC chip packages.

▲Typical implementation of the system partition mediation layer

Redistribution layer

The redistribution layer contains copper connection wires, or wires, to enable electrical connections between the various parts of the package. It is a layer of metal or polymeric dielectric material, and the bare crystals can be stacked in the package, thus narrowing the I/O spacing of large chipsets. Redistribution layers have become an integral part of 2.5D and 3D packaging solutions, enabling chips on them to communicate with each other using intermediary layers.

▲Integrated encapsulation using a redistribution layer

TSV

TSV is a key enabling technology for 2.5D and 3D packaging solutions that fill wafers with copper to provide vertical interconnect through bare silicon wafers. It runs through the entire chip to provide an electrical connection, forming the shortest path from one side of the chip to the other.

Through holes or holes are etched to a depth from the front of the wafer, then insulated and filled with a conductive material (usually copper) deposited. After the chip is manufactured, it is thinted from the back of the wafer to expose the through-hole and deposited metal on the back of the wafer, thus completing the TSV interconnection.

▲In a TSV package, the DRAM chip is grounded, penetrated, and connected to the electrodes