Basic knowledge of planar CMOS process

Typical 2D planar transistor fabrication steps are shown in Figure 1. CMOS devices are typically manufactured on a P-type <100> silicon substrate, which has a P-type epitaxial layer on which the device is formed. The epitaxial layer is a heat treatment process that reacts with hydrogen at about 1200°C and grows a silicon single crystal layer on a silicon substrate.

First, the previous process
1.1 Gaskets and silicon nitride
The first step in the CMOS process is to form a silica liner on top of the hydrogen-passivated epitaxial layer (see Figure 2). The oxide reduces any crystal dislocation created by the stress between the wafer and the subsequent silicon nitride layer. The Pad Oxide must have a high resistivity (>1020 Ohm-cm), a high band gap (~9 eV), and a high breakdown field strength (>10MV/cm). In addition, they are highly etching selective to HF, an ideal feature in device fabrication. The oxide has a thickness of 10 to 50 nm and is usually grown using a dry oxidation process. Next, another layer of silicon nitride is deposited on top of the liner. This layer acts as a stop layer for the chemical-mechanical polishing (CMP) step later in the process. Silicon nitride films can be deposited using a low pressure chemical vapor deposition (LPCVD) process.

1.2 Shallow slot isolation

In CMOS devices, shallow grooves filled with dielectric insulators are used to electrically isolate the active regions of the NMOS and PMOS. The silicon nitride layer is patterned using a lithography process.
The first step in lithography is to deposit a layer of photoresist. Photoresist are photosensitive organic materials that dissolve more (positive) or less (negative) in the selected solvent after exposure to the appropriate wavelength of light. Photoresist is applied using a process called spin coating. The wafer rotates at a high angular speed (5000 rpm) while a viscous liquid solution of the photoresist is injected into the center. Centrifugal force will drive the photoresist solution to the edge and deposit a photoresist coating of very uniform thickness on it. The target thickness of this layer varies depending on the CMOS process.
After the photoresist layer is formed, it is "soft baked" at high temperatures to remove the solvent that dissolves the photoresist. Once the lithoresist layer is dry, it is patterned using light exposure. Typically, CMOS processes use ultraviolet light (UV) and step and repeat patterning using tools called "steppers." After exposure, the wafer with the photoresist needs to be baked again to further harden the photoresist layer left in the unexposed area. Next, a development step is performed, which dissolves the photoresist in the exposure area to form the desired pattern on the silicon nitride layer in accordance with the mask.

Once the mask is formed, isolation grooves can be created (see Figure 3). This is done by backfilling the trench by etching it into the silicon substrate and then depositing silica. The wafer (including the photoresist and the underlying silicon nitride) is first subjected to a plasma etching process to remove material from those areas not covered by the photoresist (silicon nitride, substrate and epitaxial layer) to form a trench.
We need a range of plasma chemistry to etch these different materials. The silicon nitride layer is removed using fluorine etching, which uses sulfur hexafluoride as a fluorine source. The substrate layer is also removed using fluorine etching, but using carbon tetrafluoride as the fluorine source. Finally, a mixture of ethylene difluoride and sulfur hexafluoride is used as a fluorine source to remove silicon from the epitaxial layer. The reason for these different chemical compositions is the need to optimize the etching rate and etching direction of each removal layer.
After the groove is formed, the photoresist layer is removed using a plasma "stripping" process (also known as ashing), followed by a wet cleaning process. The subsequent silica trench filling step uses a high-density plasma chemical vapor deposition (HDP-CVD) process and organosilicon (TEOS) reacts with ozone. The flowable chemical vapor deposition (FCVD) process can be used at process nodes above 14nm, replacing TEOS oxide trench filling.

The final step in the shallow groove isolation process is chemical mechanical polishing (CMP) to establish a smooth, flat surface suitable for further processing (see Figure 4). The silicon nitride layer acts as a "stop layer" and prevents excessive removal of oxides in the shallow tank. After the CMP, phosphoric acid is used to remove the remaining silicon nitride at 140°C, and hydrofluoric acid is used to remove the liner, and finally a new oxide layer is grown on the exposed silicon surface using a dry thermal oxidation process.