Make 3nm Chip with DUV Lithography Mechanism!

The launch of Huawei hisilus Kirin 9000S indicates that China has been able to use DUV lithography technology to achieve 7 nm node chip manufacturing, which raises the question: how far can DUV lithography technology go through multiple exposure methods?

According to semiwiki, the latest publication of CSTIC 2023 points out that the Chinese research team is currently considering expanding DUV-based multi-patterning to 5 nanometers, and even considering using six masks in one layer. Comparing the DUV and EUV based approaches when advancing to 3 nm leads to an interesting conclusion.

LELE lithography

The most basic form of multiple patterning is the so-called "lithograph-etch-lithograph-etch" (LELE) method, which essentially involves two etchings after basic lithography.

When the second feature is inserted between the two printed first features, this halves the pitch. By extension, LE3 (3xLE) and LE4 (4xLE) may follow. However, with the advent of self-aligned interval lithography, the use of these methods to reduce the spacing to less than half the original spacing has fallen out of favor.

Self-aligned Interval lithography (SADP)

The advantage of self-aligned spacer layer patterning over LELE is that no additional lithography steps are required, resulting in additional cost savings. Spacing deposition and subsequent etching, as well as gap filling and subsequent etching, replace the lithographic sequence of coating, baking, exposure, baking, development. Although the cost is greatly reduced, precise process controls such as spacer layer thickness and etching rate selectivity are still required. The application of a one-time interval layer can achieve feature doubling within a given interval. Therefore, this is often referred to as self-aligned double patterning (SADP). Reapplication results in self-aligned quadruple patterning (SAQP), which is also expected.

Subtractive Patterning

While both LELE and SADP naturally add features to the pattern, it is sometimes necessary to remove parts of these features in order to make the final layout. The cut mask represents the area where the line segment needs to be removed. These areas are also referred to as block locations when the block line is etched. The reverse mask is called a retention mask. If adjacent lines can also be etched, limiting broken lines to a single line width creates placement problems. If alternate lines can be arranged with different etched materials, broken lines can be made with better tolerances (Figure 1).

            Figure 1. Self-aligned block/Cut removes only the portion of the alternate line

For a given interconnect, the distance between interrupts is expected to be at least two metal pitches. Therefore, when the metal spacing is 1/4 to 1/2 of the resolution limit, two masks are required per line.

              Figure 2. Two sets of etchings require two sets of block/cut masks

Alternate line arrangement

Alternate lines can be arranged naturally through LELE, SADP, SAQP, or SALELE (self-aligned LELE), a hybrid of LELE and SADP. SALELE has been recognized as the default for the narrowest metal-spaced EUV.

DUV and EUV cost assessment

Compared to EUV, the cost of DUV multimodeling has been rising. Now it's time for a renewed reassessment. First, we use the latest cost estimation (2021) normalization model (Figure 3).

Figure 3. Patterned standardization costs

Next, we use the representative schema styles of DUV and EUV for each node (Figure 4).

Figure 4 DUV and EUV model costs and nodes

A few points need to be noted:

For a 7nm DUV, the 40nm spacing is the only point at which the features of the lines can be distinguished, so the lines must be cut in a separate exposure.

For 7nm EUV, separate wire cutting is used because at 40 nm spacing, the required resolution (~20 nm) is less than the point spread function (~25 nm) of the EUV system. Due to the limitation of focal depth and pupil filling, the high numerical aperture EUV system also has no advantage for this spacing.

For 3/5nm DUV, the LELE SADP is more flexible than the SAQP at intervals below 40nm.

For 3/5nm EUV, the driving force for using LELE is the random behavior at <17 nm half-spacing and <20 nm isolation linewidth. As we approach the size of 10 nanometers, electron scattering dose-dependent blurring will also become prohibitive. The optical resolution of the system (i.e., NA) is no longer important.

Pattern shaping is not considered a way to eliminate cutting, as this would make pre-shape lithography more difficult (Figure 5). In addition, tilted ion beam etching is often used to smooth out pre-existing areas, reducing the height of the etching mask.

Figure 5. For pattern forming, the pattern before forming is very unsuitable for lithography.

In most cases, we can directly tell that DUV LELE is much cheaper than EUV single exposure (SE). In addition, DUV LE4 is cheaper than EUV dual patterning. Although LELE requires additional steps compared to SE, there are also EUV system maintenance versus DUV system maintenance and energy consumption to consider. DUV LELE uses half the energy of EUV SE, DUV SADP about 2/3, and even DUV LE4 uses only 85% of the energy of EUV SE.

All of this highlights the growing costs of moving to advanced nodes, regardless of whether you choose DUV or EUV.