TSMC packaging, a major change!

Multiple people familiar with the matter told Nikkei Asia that TSMC is working with equipment and material suppliers to develop the new approach, although commercialization could take several years. Six people familiar with the matter told Nikkei Asia that the idea behind the new approach is to use a rectangular, plane-like substrate rather than the traditional round wafers currently used, which would allow more sets of chips to be placed on each wafer.



The research is still in its early stages, but it represents a significant technology shift for TSMC, which previously considered using rectangular substrates too challenging. To make the new method work, TSMC and its suppliers must invest a lot of time and effort in development, and upgrade or replace a large number of production tools and materials.



According to people familiar with the matter, the rectangular substrate currently being tested is 510 mm x 515 mm, and the usable area is more than three times that of circular wafers. The rectangular shape also means there will be less unused area left at the edges, the sources said.



TSMC's advanced chip stacking and assembly technology - used to produce AI chips for Nvidia, AMD, Amazon and Google - uses 12-inch silicon wafers, the largest silicon wafers available today. The chipmaker is expanding its advanced chip packaging capacity in Taiwan to meet runaway demand. The Taichung plant expansion is primarily for Nvidia, while the Tainan plant expansion is for Amazon and Amazon's chip design partner Alchip, according to people familiar with the matter.



When asked about this, TSMC said it "closely follows the progress and development of advanced packaging, including panel level packaging". The company said it does not comment on individual clients.



Once seen as a relatively low-tech aspect of chip manufacturing, chip packaging technology is becoming increasingly important for maintaining the pace of semiconductor progress.



For AI computing chips such as Nvidia's H200 and B200, using the most advanced chip production techniques alone is not enough. The advanced chip packaging technology CoWoS (Chip on Wafer packaging) pioneered by TSMC is also necessary. For example, for the B200 chipset, CoWoS can combine two Blackwell graphics processing units and connect them with eight high-bandwidth memory (HBM) for fast data throughput and accelerated computing performance.



But as chip sizes continue to grow to accommodate more transistors and integrate more memory, the current industry standard - 12-inch wafers measuring about 70,685 square millimeters - may not be able to efficiently package cutting-edge chips in a few years.



For example, only 16 sets of B200s can be made on a single wafer, according to chip industry executives, and that's assuming a 100 percent production yield. Morgan Stanley estimates that about 29 of the early H200 and H100 chips could be packed onto a single wafer.



"The trend is positive. Package sizes are only going to get bigger (as chipmakers squeeze more computing power out of chips used for AI data center computing), "a chip executive told Nikkei Asia. "But it's still early days. For example, coating a newly shaped substrate with photoresist in a cutting-edge chip package is one of the bottlenecks. It takes the deep pockets of chipmakers like TSMC to push device makers to change device designs."



Display and PCB makers are experts at handling rectangular substrates, but chip production requires a higher level of equipment and material precision, industry executives and analysts say.



Mark Li, semiconductor analyst at Bernstein Research, said TSMC may need to consider using rectangular substrates soon because AI chipsets will require more and more chips in each package.



"This transition requires a massive revamp of the facility, including upgrading robotic arms and automated material handling systems to handle different shapes of substrates," Li said. "This is probably a long-term plan of five to 10 years, not something that can be achieved in the short term."



Intel is also working with suppliers to explore panel-level packaging, while Samsung, which has display-manufacturing expertise, has also experimented with new chip packaging methods.



Some companies, such as Powertech Technology, a chip packaging and testing provider, have invested in panel-level chip packaging technology. Display panel makers such as boe Technology Holdings and Taiwan's Innolux are also allocating resources to developing panel-level chip packaging technology as part of their efforts to enter the semiconductor industry.