UCie testing chip, the world's first

UCie testing chip, the world's first

Recently, Synopsys and Intel have developed the first testing chip using the Universal Chiplet Interconnect Express (UCIe) protocol, designed to connect chiplets manufactured using different processes.

The testing chip demonstrates UCIe traffic between Synopsys UCIe PHY IP and Intel UCIe PHY IP, utilizing Synopsys VCS functional verification tools to simulate each testing chip.

Intel's testing chip, Pike Creek, is composed of Intel UCIe IP small chiplets manufactured based on Intel 3 technology and is paired with Synopsys UCIe IP testing chips manufactured using TSMC N3 process. The successful pairing simulates chip mixing and matching that may occur in real-world multi-chip systems, indicating the feasibility of this approach in a commercial context.

The combination of devices built on different process technologies is crucial for increasing system complexity within a single package using the UCIe protocol.

Manuel Mota, Senior Product Manager for High-Speed Interface IP at Synopsys Solutions Group, stated that this collaboration revealed valuable lessons, and they plan to share these experiences with the UCIe Alliance.

As silicon manufacturing takes a long time, and validating whether everything works as expected incurs significant costs and time, finding a way to assess compatibility using existing testing chips or silicon could be a good method.

Designing multi-chip systems involves extensive planning, especially when reusing packaging or circuit board designs. Building as much flexibility on the circuit board as possible is one way to provide options for future use.

Open standards like UCIe provide confidence in interoperability. When a company controls both ends of the link, there is, of course, no concern about whether each party will cooperate. However, looking ahead, in the next few years, it is expected to see more companies unwilling to build both sides simultaneously, opting instead to purchase components from the market that likely use different manufacturing technologies. This was emphasized at the recent DVcon Europe Small IP Group meeting.

By allowing design partitions to include multiple process nodes, small chiplets help reduce manufacturing costs for advanced nodes. Mota stated that without standards, IP availability is limited, and choosing process nodes based on IP availability is not the best approach. UCIe testing chip interoperability demonstrations provide solid evidence for mixing and matching IP designs and lay the foundation for an open small chip ecosystem.

One of the advantages of multi-chip system architecture is that it can consist of chips from different vendors for different process nodes. This provides flexibility in terms of cost as well as optimizing power, performance, and area (PPA). UCIe is a key element in combining different components, enabling them to communicate with each other while supporting a range of advanced packaging technologies.

While UCIe-compliant multi-chip systems may run well during development, testing, and manufacturing, the project needs to ensure that chip-to-chip connections remain reliable from the outset and in the field. This is where UCIe IP plays an indispensable role.

UCIe IP typically consists of a controller for achieving low-latency communication between chips based on common protocols (such as PCIe, CXS, and streaming protocols); a PHY for high-performance and low-power connections within the package; and verification IP to accelerate verification convergence. Built-in testability features allow you to eliminate defective chips during the bare die testing phase. In addition to these testability features for known-good chips, IP can also provide cyclic redundancy check (CRC) or parity check for error detection and retry functions for correcting detected errors.

Intel indicates plans to continue collaborating with Synopsys to further develop its UCIe technology, emphasizing the close cooperation of the entire semiconductor ecosystem is crucial for chip designers to achieve the advantages of these complex, interdependent designs.