Why Develop Advanced Packaging?

What is Moore's Law?
In 1965, Intel co-founder Gordon Moore made a prediction that the number of transistors on an integrated circuit would roughly double every 18 months. This law has been the guiding principle of the semiconductor industry over the past few decades.

What are the problems caused by too small line width of the chip?
1, transistor size is gradually approaching the physical limit, the current most advanced chip process has reached about 2nm, close to the size of a single atom, further reduction is becoming more and more difficult. At this time, the quantum tunneling effect will be very obvious, the short channel effect, leakage current and other problems are becoming more prominent, and the overall performance of the chip will be greatly reduced.
2, the manufacturing cost is greatly increased. The manufacture of a chip with a smaller linewidth has more stringent requirements for the factory, semiconductor equipment, and materials, and requires greater investment. The cost of building a 2nm plant with a monthly output of 50,000 wafers is about $28 billion (about 1998 billion yuan), while the cost of a 3nm plant with the same capacity is about $20 billion (about 142.7 billion yuan).
3, with the increase of transistor density, power consumption and heat dissipation problems become more prominent.
Therefore, advanced packaging has become an important path for the development of integrated circuit technology in the post-Moore era.

Why can advanced packaging make short board?
1, advanced packaging can greatly improve the integration. Vertical stacking can integrate multiple chips in the vertical direction, greatly reducing the package area.
2, through TSV or TGV technology to achieve short-distance interconnection between chips, reducing the path and delay of signal transmission
3, short-distance interconnects reduce the power required for signal transmission, reducing the overall power consumption.