The document discusses common cleaning methods and technologies in semiconductor manufacturing. It first introduces the advantages of dilute chemical cleaning methods, such as reducing chemical consumption and optimizing cleaning step times. It then introduces the IMEC cleaning method, as well as its applications in single-wafer and dry cleaning. Dry cleaning removes impurities from the wafer surface using chemical vapor techniques, avoiding the generation of waste liquids, but still requires combination with wet cleaning. The document also emphasizes the importance of cleaning effectiveness in semiconductor manufacturing and proposes further research into cleaning technologies to address process variations. Read More

AMD, positioned as NVIDIA's main competitor, surges in the AI chip market with its MI300 chip offering superior performance and power efficiency. Mark Papermaster, AMD's CTO, highlights their commitment to open sourcing, enabling collaboration and innovation. Emphasizing energy efficiency amidst supply constraints, AMD focuses on heterogeneous computing to tailor solutions for various applications. Looking ahead to 2024, AMD plans widespread deployment of AI capabilities across its product range, from cloud to gaming devices, emphasizing open-source principles and strong partnerships for continued success. Read More

The information is sourced from the official account "SiP and Advanced Packaging Technology" on a social media platform, authored by Suny Li. The article introduces "3.5D packaging" in advanced packaging, debunking the notion of it being a mere gimmick. Suny Li explores terms like 2.5D, 3D, Hybrid Bonding, and HBM, detailing their significance.
In summary, 2.5D utilizes an interposer layer with TSVs, while 3D achieves direct chip interconnects through TSVs. Hybrid Bonding enhances interconnections, and HBM combines 3D and 2.5D TSVs for stacked memory chips.3.5D is presented as 3D+2.5D with Hybrid Bonding support, eliminating the need for bumps in 3D TSV interconnection. The article sees 3.5D as a new era in packaging, leading to classification updates that now include 3.5D alongside 2D, 2D+, 2.5D, 3D, and 4D. Read More

The global semiconductor industry is gradually emerging from a downturn, with executives from companies like Intel, TSMC, and Samsung expressing confidence. Despite a 38% YoY decline in Samsung's net profit in Q3, gradual recovery in customer inventories and production cuts alleviating oversupply offer optimism. The semiconductor market's revival is reassuring for the U.S. government, investing billions to expand chip production. While semiconductor manufacturers are rebounding from last year's boom, executives caution that the recovery may not be as swift as in 2021. PC chip performance exceeded expectations, but weak smartphone demand and a slowdown in electric vehicle sales are noted. However, demand is expected to rebound in enterprise server clusters and AI computing. The global semiconductor industry is projected to surpass $1 trillion in revenue by 2030, injecting new momentum into the global economy. Read More

In brief, automotive high-performance computing stands at a crucial evolutionary juncture. Faced with the constraints of Moore's Law, the industry must embrace innovation, explore new technological avenues, and devise design concepts to adapt swiftly. The future landscape holds immense potential, especially with the emergence of Domain-Specific Architecture (DSA) and the widespread use of customized chips in automotive applications. Notably exemplified by Tesla's FSD chip, DSA plays a pivotal role in areas like autonomous driving. This prompts automotive manufacturers to actively pursue innovations aligned with emerging trends. The current crossroads present unprecedented possibilities for automotive high-performance computing, marking a transformative era for future technologies and intelligent transportation. [Reference: McKinsey - "The Future of Domain-Specific Architecture and Computing"] Read More

Recently, Synopsys and Intel have developed the first testing chip using the Universal Chiplet Interconnect Express (UCIe) protocol, designed to connect chiplets manufactured using different processes. Read More